Power Optimisation for Embedded SysTems

 Project Highlights

• FP6 WorkProgram Objective: Microelectronics design and test
• EU funding: € 3,547,635
• Estimated costs: € 6,123,949

Project Goals

• Develop a new design methodology and tool suite for power estimation and optimisation in heterogeneous embedded SoC designs
• Enable design space exploration for low power system architectures, algorithm optimisations and system partitioning
  

CEFRIEL Contribution

• Development of a methodology for the optimization of the application SW power-consumption
• Development of a tool suite that implements the methodology for various HW/SW platforms
  

Project Consortium

• C 1 Kuratorium OFFIS e.V. (Germany)
• CEFRIEL (Italy)
• Politecnico di Torino (Italy)
• Alcatel SEL (Germany)
• ARM Limited (United Kingdom)
• OSC-OFFIS GmbH (Germany)
• BullDAST s.r.l. (Italy)
• ChipVision AG (Germany)
• ATMEL (France)
• Motorola (Switzerland)